Plenary Session

This session covers "STT-MRAM technology and exploratory devices" and consists of six papers. The first four papers are on the state-of-the-art STT-MRAM technology and the last two papers are on exploratory STT-MRAM devices to address the switching current and scaling challenges for next generation MRAM applications. The first paper offers new application opportunities of eMRAM combined with CMOS Image sensor at 28nm logic platform. The second paper presents a design scheme to improve write energy and write speed of STT-MRAM cells, essential for MCU applications. The third paper demonstrates MRAM data scrubbing solutions for the last level cache applications. The fourth paper is an invited paper, reviewing technology-design-co-optimization solutions for emerging eNVMs to achieve manufacturability with a competitive PPA and required reliability. The fifth paper demonstrates that MTJ switching current can be reduced by 2x without sacrificing TMR using a new device structure -double spintorque magnetic tunnel junction. The last paper demonstrates switching of ultra-small MTJ (sub-5 nm) with 3.5 ns write pulses, by controlling the bulk, shape, and interfacial anisotropies.