Design and Verification of Large-Scale Computers by Using DDL

197915 citationsJournal Article

Authors

Nobuaki Kawato · Fujitsu (Japan)

T. Saito · Fujitsu (Japan)

F. Maruyama · Fujitsu (Japan)

T. Uehara · Fujitsu (Japan)

Abstract

This paper describes the total support system for DDL which has been approved by design engineers at Fujitsu. A simulator is used not only at register transfer level but also with gate level description. The translator generates gate level designs which are then optimized by designers. The verifier has powerful functions to detect conflicts in specification and its implementation.

Topics & Keywords

Embedded Systems Design Techniques Formal Methods in Verification Parallel Computing and Optimization Techniques

UN Sustainable Development Goals

Industry, innovation and infrastructure

Publication Details

Volume 26, pp. 360-366

DOI: 10.1109/dac.1979.1600137

Field-Weighted Citation Impact: 5.60