Conception et réalisation de l'unité de décision du système de déclenchement de premier niveau du détecteur LHCb au Large Hadron Collider (LHC)

The LHCb experiment is installed at the Large Hadron Collider at CERN. In order to reduce the amount of data storage, a trigger system is required. The Level-0 Decision Unit (L0DU) is the central part of the first trigger level. It is a full custom 16 layers board using advanced FPGA. The L0DU receives information from the Level-0 subtriggers via high speed optical links running at 1.6 Gb/s. The processing is implemented using a 40 MHz synchronous pipelined architecture. It performs a simple physical algorithm to compute the trigger decision in order to reduce the data flow down to 1 MHz for the next trigger level. The design FPGA is mainly composed by a Partial Data Processing (PDP) and a Trigger Definition Unit (TDU). The aim of the PDP is to adjust the clock phase, perform the time alignment, prepare the data for the TDU and monitor the data processing. The TDU is flexible and allows to fully reconfigure all the trigger conditions without any re-programming the FPGA.