A 3-8bit Reconfigurable Hybrid ADC Architecture with Successive-approximation and Single-slope Stages for Computing in Memory

Computing in Memory (CIM) is reported as one of the most promising non-Von-Neumann computing architectures to replace the existing digital AI processor architecture. Compared with digital-based computation, CIM shows advantages in computing density, energy efficiency, and throughput. However, it requires a large analog-to-digital array to quantize the column-parallel analog Multiply-Accumulate (MAC) results with tight area, high speed, and low power requirements. In this paper, we first discuss the design trade-off between different ADC architectures for CIM accelerators. To improve the overall system efficiency, a 3-8bit reconfigurable hybrid ADC architecture with successive-approximation and single-slope stages is proposed, particularly emphasizing the reconfigurability of the conversion speed and bit-resolution for different computation mode. A prototype is designed and simulated in 65-nm CMOS, which occupies an area of l90$\mu$m $\times$ 5$\mu$m and consumes a power of 48$\mu$W at 8-bit conversion mode, achieving 7.87-bit ENOB and 10.2 fJ/conv.