Hardware Architectures for Digital State Space Controllers

Two hardware buffer architectures for digital state feedback controllers based on controllable canonical model are presented. One is linear buffer architecture and the other is circular buffer architecture. The architectures take advantage of cascaded structure of the canonical form to simplify state calculations. At each sampling time, only the n-th state needs to be re-calculated. This makes the architecture a lot simpler than full state calculation method. For linear buffer architecture, a new “backtapping” technique is introduced to sneak in state shifting during multiplication. For circular buffer architecture, “address mapping” is used to map linear state addresses to coefficient addresses. The buffer architectures simplify hardware realizations of modern state space controllers and provide low-cost low-power solutions to multiple control systems needed in applications such as self-driving and robotics technologies.