Trigger Timing Interface for the Read-Out Upgrade of the Belle II DAQ

To improve the data throughput of the Belle II data acquisition (DAQ), we are upgrading the central processing unit (CPU)-based COPPER system with a PCIe40 board carrying an Arria 10 field-programmable gate array (FPGA). Since one of the main functionalities of the new system is event building in the FPGA, the read-out system must be synchronized with the front-end electronics. This task is performed by the bidirectional trigger timing distribution system. During system commissioning, we prepared several versions of the interface to this system. In the initial version of the interface, we ported the code from Xilinx FPGAs to Arria 10. This revision also introduces monitoring of the status for multiple channels and a ring buffer to distribute trigger information to all channels in parallel. To improve stability under external noise, we implemented a clock-data recovery (CDR) using an independent onboard oscillator as a reference clock in the next revision of the interface. We are also developing a version utilizing a high-speed serial transceiver to replace CAT-7 RJ45 cables with optical fibers. The system commissioning started in 2021 with a few detectors and will be completed after the long shutdown 1 of SuperKEKB in 2023. In this article, we present the architectures of the interface to the trigger timing system implemented in the PCIe40 board and the system performance in the experiment.