Optimization of a 65 nm CMOS imaging process for monolithic CMOS sensors for high energy physics

The long term goal of the CERN Experimental Physics Department R&D on monolithic sensors is the development of sub-100nm CMOS sensors for high energy physics. The first technology selected is the TPSCo 65nm CMOS imaging technology. A first submission MLR1 included several small test chips with sensor and circuit prototypes and transistor test structures. One of the main questions to be addressed was how to optimize the sensor in the presence of significant in-pixel circuitry. In this paper this optimization is described as well as the experimental results from the MLR1 run confirming its effectiveness. A second submission investigating wafer-scale stitching has just been completed. This work has been carried out in strong synergy with the ITS3 upgrade of the ALICE experiment.