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Diversity in packaging for a strong supply chain requires higher performance and lower cost processes for new manufacturers. Six-side protected, aka “6S or fully protected”, CSP is an emerging and rapidly growing market. Fully protected CSP (without substrates or lead-frames) was first implemented with processes such as M-series and eWLB. These processes require costly and complex die reconstitution, expensive tapes, molding, and other operations most common to FO to obtain 6-side die protection. These steps can be eliminated in a wafer level process to provide high-performance low-cost P-WLCSP to enable new CSP manufacturing capability, Fan-In and Chiplets. American Semiconductor’s Semiconductor-on-Polymer (SoP) 300mm SoP-TM, a P-WLCSP process, is an advanced packaging process optimized for protected CSP, fan-in, and chiplets. Protected FI process innovations can improve performance in power devices, RF switches, photonic IC (PIC), die stacking, and thin board applications. This paper builds on the SoP-TM process development provided at the IMAPS Symposium earlier this year with the addition of first silicon data for electrical test chips. SoP-TM test chip features include 10um silicon thickness, metal interconnect and micro-bumps, smooth silicon sidewalls and 6-side polyimide encasement. Reliability data and testing is a key area of investigation for thin-device technology. Ultra-thin device reliability test methods under consideration for new NIST standards will be presented. Mechanical, high temperature and high humidity reliability for SoP-TM test chips, Chip-on-Flex (COF) and Flip Chip using the new test methods will be presented.