Demonstration of a Wafer-level Integration for System-on-Wafer Architecture

As one of the most important advanced packaging technologies, heterogeneous integration is desired to help advanced node to cover the integrated systems’ memory wall to further continue Moore’s law. With continuous growing demands for high performance computing, multi-chip wafer level integration is developed for artificial intelligence. By shrinking the interconnection distance and enlarging the integration scale, System-on-Wafer (SoW) is a promising architecture for improving the integration system performance. In this paper, a wafer level integration with historically large scale of over 200 dies and 1 million bumps are assembled on a 12-inch Si wafer substrate for SoW process demonstration. A 100% yield of flip chip (FC) bonding and good warpage control are demonstrated. Besides, fine FC space and high integration density are also acquired. This work proposes a novel SoW architecture and process flow solution for wafer-level integration product in the post Moore’s law era.