Cell to Core-Periphery Overlap (C2O) Based on BCAT for Next Generation DRAM

The ongoing trend of DRAM design rule scaling has faced with serious challenges. This paper focuses on sustaining the scaling momentum by introducing Cell to Core-Periphery Overlap (C20) based on Buried Channel Array Transistors (BCAT). This approach enables bit growth and bit cost reduction with less scaling and introducing wafer bonding technique. Moreover, by expanding the core area and reducing mismatch, we significantly enhance sensing characteristics, thereby relaxing the storage capacitance burden. Additionally, stress-induced experiments by the wafer bonding process demonstrate that these improvements do not adversely affect the performance of DRAM core-periphery transistors.