MexSIC-TDC, A Mixed-Mode Readout ASIC for SiPM TDC Measurements with a 48.82 ps Resolution

This work presents a mixed-mode readout ASIC, the MexSIC-TDC, aimed at SiPM output time-todigital (TDC) measurements. The proposed ASIC is mainly composed of an analog front-end, a 48.82 ps resolution time-to-digital converter (TDC), and a digital back-end. The analog front-end converts the current delivered by the SiPM into a voltage using a $500 \Omega$ @ 100 MHz transimpedance amplifier. The resulting voltage is compared against an 8-bit controlled voltage reference to create a digital pulse, the width which is proportional to the voltage reference level and the SiPM’s current pulse duration. The digital pulse is used to trigger an edge detector which enables two up/down 6-bit hit registers that captures two digital words coming from a delay-line loop (DLL).These two words are the time stamp of the rising/falling events. The DLL consists of a 64stage Meneatis cell delay-line with a time reference provided by a 320 MHz clock that comes from a 1.28 GHz LC-tank phase-locked loop (PLL) and a 4 x frequency divider. The PLL uses a 40 MHz reference clock. The PLL, DLL, and hit registers conform the TDC. The digital back-end uses the up/down words and a 10-bit coarse counter for ToF calculations, leading to a maximum timewindow of $3.2 \mu \mathrm{s}$. All data is stored in two 7-bit depth 16-bit FIFO memories that send their content through a 80/160 MHz serializer. In addition, the digital back-end performs frequency/time corrections in the PLL and DLL during the calibration start routine using an $\mathrm{I}^{2} \mathrm{C}$ protocol. The MexSIC-TDC was designed in a 180 nm CMOS standard process and Cadence ${ }^{\circledR}$ software, it exhibits a $2.5 \mathrm{~mm} \times 2 \mathrm{~mm}$ silicon area, includes three fully functional channels and one calibration channel. The MexSIC-TDC is a fully integrated solution that eliminates the use of separate analog front-end integrated circuits (IC) and TDC ICs.