Analyzing Shared Cache Partitioning on an NXP P4080 Processor as a Method of Multi-Core Interference Mitigation

This paper focuses on testing and analyzing the different configurations for cache partitioning and determining how effective they are in the robust development of safety critical applications such as airworthiness applications. It also creates an experimental framework in which the system performance, stability, and determinism are all tested and measured through a series of multiple cache partitioning configurations using software and hardware metric tests with the results recorded for analysis. It aims to provide a methodology for when cache partitioning creates an advantage or disadvantage to the system based on the user's needs and development goals.