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Heterogeneous integration for system in package (SiP), flip-chip integration in 3D packaging and embedded ICs in advanced Printed Circuit Boards (PCB) are all pushing the limits for low profile packaging. Advanced polymer materials applied in Semiconductor-on-Polymer™ wafer level chip scale packaging (SoP WLCSP) are gaining traction as a high reliability ultra-thin packaging solution. The 2019 roadmap for Heterogeneous Integration defines heterogeneous Integration (HI) as the integration of separately manufactured components into a higher-level assembly that provides enhanced functionality and improved operating characteristics. The development of this technology is a significant industry challenge that can evolve quickly with the application of SoP polymer based packaging. At advanced nodes, die yield falls exponentially with die size. Splitting a large monolithic SoC into smaller tightly coupled die, is an attractive alternative considering that die cost per unit area is escalating. The smartphone industry has been an early adopter of HI technologies in the use of SiP for multiple generations, essentially for the advantages in miniaturization, modularity for co-design, and enhanced generation-over-generation performance. The application processor is almost always on the most advanced node and housed in a Package on Package (PoP) configuration with memory component(s) stacked on top of this ASIC. Teardowns of the Package-on-Package (PoP) packages for Apple XSMax, Samsung Galaxy S9+, and Huawei 20 Pro have shown the utilization and need for continued z-axis thickness scaling. Implementation of SoP CSP for package in package integration or for chip on thin PCB, interposer or flex can provide another package capability for evolution of multi-layer heterogeneous integration. Reliable ultra-thin polymerized die have the potential to tackle the third dimension (z-axis) of total IC package volume in 3D integration. SoP die can replace current full thickness or partially thinned (typically >250µm) die with <35µm package thickness devices. In addition, the SoP process has the potential to extend package roadmaps enabling smaller higher performance packages in several areas, including Fan-Out (FO). Thin bridge die could simplify localized high IO for substrates. Thin embedded IPD (integrated passive devices) have the potential to increase the capability and shrink the size of substrate process based passives, similar to the performance increase for wafer based devices versus printed electronics. In addition thin high IO die could allow simplified embedding in substrates. The differentiation of PCBs, interposers and flex circuits is starting to blur. Package integration within the layers of these devices can create embedded ICs that take less system space and improve system performance. Traditionally, manufacturing steps to place an IC within the board substrate vary and require space to be created for the component body, in the form of a cavity for traditional packaged ICs. In Integrated module board (IMB), components are aligned and placed inside a cavity that is routed to the core laminate by controlled-depth routing. The cavity is filled with molding polymer to ensure chemical, mechanical, and electrical compatibility with the substrate. Isotropic solder is impregnated with the polymer to form reliable solder joints when the embedded part is laminated into the stack. Polymerized ICs in SoP CSP eliminate cavity requirements and molding polymers for IMB. Chip in polymer (CIP) approaches use thin chips in built up dielectric layers of PCBs, rather than integrating them into the core layers. When SoP CSP is applied, it is feasible to achieve the same capability, but with a much smaller z-axis and without creating a surface geography perturbation. This presentation will include an introduction to SoP CSP utilizing advanced polymer technology for accelerating evolution of HI, PoP and Embedded applications.