Multiple Cell Upsets in the Configuration RAM of a 7-nm FinFET SoC Under Heavy Ions

This manuscript investigates the heavy-ion effects on the novel 7-nm FinFET Advanced Micro Devices, Inc. (AMD) (formerly, Xilinx) Versal system-on-chip (SoC), namely on the configuration memory of the embedded field-programmable gate array (FPGA). The experiment consisted of loading a program in a delidded device, irradiating in static mode and reading back the content. Several species and configurations were used to test the device. First of all, it was tested the efficiency of the soft error mitigation by Xilinx (XilSEM) tool, provided by the manufacturer to fix erroneous bits. Second, this tool was disabled to find out the cross sections of the single-event upsets (SEUs) of different multiplicities. Flipped upsets were classified using statistical techniques to reconstruct the multiple-cell upsets (MCUs). No multiple-bit upset occurred and only 4-bit MCUs were observed in the worst cases, although it is clear that the cross section of the 2-bit MCUs is comparable to that of single-bit upsets (SBUs). Later, a strategy to carry out fault injection campaigns is proposed taking into account the knowledge acquired after the radiation tests, and the expected error rates in actual space environments are studied.