Design Implementation of Synchronous FIFO-Synthesis, PNR, STA and Physical Verification

This paper presents a comprehensive methodology for the design and implementation of a Synchronous FIFO (First-In-First-Out) system, covering the entire ASIC (Application-Specific Integrated Circuit) flow from RTL (Register Transfer Level) to GDSII (Graphic Data System). The work details the critical phases involved in achieving synthesis, placement and routing (PnR), static timing analysis (STA), logic equivalence check (LEC), and physical verification, using industry-standard tools such as Cadence Genus, Synopsys ICC2, and Mentor Graphics Calibre. The design is synthesized using the Cadence Genus tool, followed by placement, clock tree synthesis (CTS), and routing with Synopsys ICC2. Static timing analysis is performed using Synopsys PrimeTime after parasitic extraction via StarRC, with necessary timing adjustments made through buffer insertion and gate sizing to meet performance specifications. Logic equivalence checks ensure functional correctness through both post-synthesis and post-route stages. Physical verification, including design rule checks (DRC) and antenna checks, is conducted using Cadence Virtuoso and Mentor Graphics Calibre to ensure manufacturability. The Synchronous FIFO design, implemented on a 180nm process node, successfully meets timing and physical constraints, and the final GDSII file indicates the design's readiness for the next steps in the chip manufacturing process. The work emphasizes the importance of a rigorous and structured design flow to optimize performance, power, area, and timing, with potential for future work in low-power optimization and scalability.