A 2.1-ns Dead Time 5-μm Single Photon Avalanche Diode with 2-Layer Transistor Pixel Technology

This study reports a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5-\mu \mathrm{m}$</tex> -pitch single photon avalanche diode (SPAD) with 2-layer transistor pixel technology. The dead time is reduced to 2.1 ns, which is 1/3 times smaller than conventional three-dimensional-stacked SPAD pixels because the 2-layer pixel technology contributes to a reduced cathode capacitance by moving a pixel front-end circuit from the bottom tier logic chip to the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2^{\mathrm{n}\mathrm{d}}$</tex> layer of the top tier pixel chip. Simultaneously, the in-pixel counter for photon counting with time-of-flight imaging function increases from 5 to 7 bits. The dark count rate and photon detection efficiency at 940 nm and room temperature are 5.0 cps and 24.4 %, respectively. We maintained the characteristics comparable to the state-of-the-art SPAD pixels even with the 2-layer pixel technology.