A 31.25 MHz bandwidth 52.4 dB SNDR VCO based ADC with on-chip non-linearity correction

This paper introduces a method aimed at rectifying nonlinearities in analog-to-digital converters (ADCs) based on voltage-controlled oscillators (VCOs). The proposed approach employs a straightforward digital logic circuit, three single-stage transistor-based circuits, and four switches to augment the linearity of the VCO tuning curve. Experimental findings from a 1.2 V, 65 nm CMOS pseudo-differential ADC reveal a no table 2. 5-bit improvement in the Effective Number of Bits (ENOB), with only marginal increases of 5.2% and 9% in total power and area, respectively.