Development and system evaluation of high-power semiconductor optical amplifiers for satellite-based free-space communications

This paper presents the work done by ORIONAS on High-Power Semiconductor Optical Amplifiers (HP-SOA) optimized for lower-end FSO communications. System-level requirements were reviewed in terms of functional performance as well as environmental constraints for such use cases. Specific design and developments in optoelectronic device structures were achieved by III-V Lab leveraging the experience and findings of a number heritage projects. HP-SOA designs were based on the Slab Coupled Optical Waveguide Amplifier (SCOWA) and fabricated using the Semi Insulating Buried Heterostructure technique (SIBH). The values of mode confinement over the quantum wells and length of components result from a trade-off between the Noise Figure (NF) and saturation power on one hand, and the overall gain on the other hand. ORIONAS SOA chips were packaged into 14-pin Butterfly modules with fiber in and fiber out and TEC and thermistor included. SOA modules were integrated by Thales Alenia Space for system-level evaluation into an optical transmission test-bed using commercial devices to establish reference performance. An SOA module was found to exhibit high-gain (> 40 dB), high output power (+21 dBm) and low noise figure (6 dB). It was subjected to system-level performance evaluation under OOK and DPSK modulation formats ay 25 Gbps rate. Performance were assessed in terms of bit error rate (BER) curve, detection sensitivity, and power penalty compared to the reference case. OOK signal suffered from significant reduction of the extinction ratio via SOA gain compression, which translates into large power penalties in detection sensitivity. A better behavior was obtained under DPSK modulation, yielding down to 2 dB power penalty in detection sensitivity. The features and performance of such HP-SOA are discussed and compared to those of their doped-fiber counterparts through experimental results. Potential use cases and possible paths, either at system or at SOA chip design level, for improving performance are briefly discussed.