Exploiting LDPC Syndrome for Multidimensional Hard-Decoding Read Retry on NAND Flash

NAND-flash-based solid-state drives (SSDs) are under constant pressure to deliver higher storage density while minimizing power and performance overhead. As the number of bits stored per NAND flash cell has scaled from single-level cells (SLC) to triple-level cells (TLC) and soon to penta-level cells (PLC), the reduced voltage margins between cell states challenge data reliability, requiring stronger decoding techniques. To maintain reliability and correct error data bits, low-density parity-check (LDPC) codes are widely deployed on these high-density devices and can operate in two modes: hard decoding, which uses threshold-based bit decisions and is relatively power-efficient, and soft decoding, which leverages additional reliability information but imposes higher computational and energy costs. In practice, NAND flash controllers initiate soft decoding when hard decoding fails, thereby preserving data integrity at the expense of latency and power overhead. Current approaches employ read-retry tables to adjust reference voltages and maximize hard decoding success rates; however, such tables cannot fully address diverse bit-error patterns, often unnecessarily invoking soft decoding and incurring significant performance overhead. To overcome this limitation, we propose a novel LDPC-syndrome-based loss function that adaptively adjusts multidimensional reference voltages, significantly reducing unnecessary soft decoding triggers without relying on predetermined read-retry tables or iterative voltage adjustments. Experimental results demonstrate that our proposed loss function effectively reduces the soft decoding trigger rate and the number of page reads, substantially minimizing the performance and power costs associated with soft decoding.