Evolution of readout ICs (ROICs): past, present, and future

The past decades have generated several ROIC advancements, emphasizing large-format focal plane arrays (FPAs). As pixel circuits continued to shrink, the need for low-noise performance without compromising frame rates led to the transition from analog to digital ROICs. This evolution introduced per-chip ADCs in the late 1990s, per-column ADCs in the 2000s, and eventually per-pixel ADCs. Today, ROIC innovation is centered on high dynamic range (HDR) designs and further pixel size reduction to achieve diffraction-limited spatial resolution across multiple infrared bands. Looking ahead, future ROIC technology will enable “smart FPAs” with diffraction-limited pixels, BLIP-level noise and well capacity, high readout rates for dynamic scene tracking, simultaneous multi-band imaging, and on-chip processing. Through 3D-IC stacking, these smart ROICs will incorporate in-pixel processing for scene-adaptive imaging, event-driven asynchronous readout, ranging, and even single-photon counting—all within a compact, low size, weight, and power (SWaP) architecture. This paper traces the evolution of ROIC technology.