Transistor-Level Simulation for Neural Network Analog Implementations

This paper presents an integrated simulation framework for mapping neural network models onto analog circuits, enabling energy-efficient inference. Our method automatically converts weights and activations into electrical parameters, generates SPICE-compatible PWL files, and simulates analog crossbar arrays implementing MAC operations with foundry-approved simulators and PDKs. We validate our approach using a bulk-modulated PMOS analog MAC cell in two applications: a single-layer network for MNIST classification and a CNN for CIFAR-10 classification.