Scan Strategies for High Quality Latch Array Testing

Latch arrays are increasingly popular in designs due to lower area overhead and power consumption compared to the alternative SRAM solution. In this paper we will visit the new scan strategies used in latch array design, its implementation flow, and the benefits of these changes to latch array test coverage. Scan solution has the advantage of smaller area overhead compared to the BIST solution. In addition, it also provides failure analysis capability, which is not available in the traditional BIST solution. It is proven that this innovative approach could achieve 100% SAF and TDF coverage for latch array core.For the surrounding logic of latch array, including BIST wrapper, due to complexity of clock gating logic and decoding logic, different latch array reset schemes are tested and compared. High quality latch array test is achievable with the proposed new scan strategies for latch array.