Transient Current Peak Investigation in an Inverter Leg with Paralleled GaN FETs

This paper addresses the critical issues in parallelising GaN FETs for high-current switches in low-voltage power converter applications, such as light e-mobility, humanoid robotics and battery chargers. While parallel connection enhances power handling and efficiency, it introduces significant challenges like unequal current sharing due to device parameter variations and asymmetrical layouts in static and dynamic conditions. The paper investigates these constraints using a dual approach of LTSpice simulations and experimental validation. An experimental board composed of four switching legs with independently controlled gate voltage and time delay for each parallel device is developed, allowing accurate emulation of various parameter spread conditions. These combined simulations and experimental analyses comprehensively investigate the behaviour of GaN transistors in parallel configurations under real-world operating conditions. It aims to demonstrate the feasibility of high-current GaN FET power boards and increase the knowledge of designing GaN FET modules by considering both transistor parametric spread and layout optimisation.