Virtual fabrication of a 3nm gate all around inverter

Background: This study investigates the use of a Digital Twin to study a virtual 3 nm process node inverter built with Gate-All-Around transistors. Aim: Investigate the interaction of processes to build a virtual inverter and simulate it for electrical performance. Approach: A 3 nm process node was simulated using stochastic models. Overlay variation was introduced to the layout to study layer to layer interactions. Results: The Digital Twin flow found three problems when building virtual inverters. Two problems were associated with interactions between layers, and one was a single layer problem. A fix for these problems was generated and tested. Conclusions: The digital twin enables learning beyond the simulation of individual processes using traditional stand alone methods. Two virtual device problems due to layer to layer interactions were identified. A third problem on a single layer was identified using stochastic simulations. A fix was introduced that resolved the three problems but increased the device resistance. These results enable an engineer to commit to the fix or continue investigating new fixes prior to committing to wafer testing, which should reduce the required testing cycles.