Mechanical Sample Preparation of Heterogenous Devices - Evaluating SOC Relaxation When Removing Chiplets

Abstract Heterogeneous technology has evolved significantly from its origins in multi-chip modules to advanced packaging techniques that integrated separately manufactured components into a unified system. This paradigm, often described as “More than Moore,” allows for the continued scaling of performance beyond traditional transistor miniaturization. While integration of functionally diverse components, often fabricated at different process notes, into a single package offers system-level advantages, it introduces new challenges for both electrical and physical failure analysis. This study investigates the mechanical effects of die relaxation during deconstruction by systematically removing individual chiplets and tracking curvature changes in the SoC die. The goal is to develop a reliable strategy for sample preparation that minimizes stress induced damage during failure analysis. Curvature evolution was explored across a range of 2.5D and 3D heterogeneous devices featuring various chiplet configurations and the presence or absence of stiffener rings.