Implementation of transformer-based LLMs with large-scale optoelectronic neurons on a CMOS compatible platform

The recent rapid deployment of data center infrastructures for performing large language models (LLMs) and related artificial intelligence applications in the cloud is predicted to incur exponentially growing energy consumption in the near-term future. In this paper, we propose and analyze the implementation of the transformer model, which is the cornerstone of the modern LLMs, with novel large-scale optoelectronic neurons constructed over a complementary metal–oxide–semiconductor (CMOS) compatible platform. With all of the required optoelectronic devices and electronic circuits integrated in a chiplet only about 2 × 3 cm2 in size, 175 × 109 parameters in the case of GPT-3 are shown to perform inference at an unprecedented speed of 12.6 POPS using only a 40 nm CMOS process node, orchestrated by an optoelectronic reinvention of systolic array with no data skew and negligible propagation delay, along with a high power efficiency of 74 TOPS/W and a high area efficiency of 19 TOPS/mm2. The influence of quantization formats and hardware-induced errors is numerically investigated and is shown to have a minimal impact. Our study presents a new yet practical path toward analog neural processing units (NPUs) to complement existing digital processing units.