PV-Bit: Private Verification of FPGA Bitstreams Via Bitstream Equivalence Checking

Established FPGA design verification flows utilize sophisticated methods to provide assurance for microelectronic designs deployed on FPGA based systems, but they lack visibility into the vendor proprietary configuration bitstream format. This means the assurances they provide only extend as far as the post place and route simulation netlist, leaving a verification gap where errors or malicious modifications could be introduced during the bitstream generation process. Here, we discuss and evaluate the operation and efficacy of PV-Bit as a tool that can address this gap via Bitstream Equivalence Checking: proving physical (and thus functional) equivalence between the bitstream and a verified, trusted netlist. PV-Bit uniquely performs this check without exposing private Intellectual Property included in the bitstream.