Automated MATLAB™-to-HLS Conversion and Exploration for DoD ASIC/FPGA Development

While relatively new when compared to more traditional RTL design entry methods, high-level synthesis now has two decades of successful tapeouts. However, its use with MATLAB was a manual process. Many HLS designs begin as MATLAB models which must first be rewritten by hand in SystemC before they can be turned into hardwareThis paper recounts our experience using a new automated flow available in MATLAB’s HDL Coder app. With this flow, we automatically converted our MATLAB code files into SystemC modules and ran them through the Cadence<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">©</sup> Stratus™ High-Level Synthesis (HLS) tool. We also used Cadence<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">©</sup> Cerebrus™ Intelligent Chip Explorer, a machine learning tool that works with Stratus HLS, to define an exploration space and let it find the gate-level result with the very best area and power. With this approach, we ultimately exceeded the PPA results for an earlier handwritten, manually explored SystemC version of the same design.