On-Silicon Characterization of CDM-Like Stress in Long Interconnects Using vf-TLP in Nanometric ICs

This work presents a comprehensive silicon-based validation methodology for Charged Device Model Electrostatic Discharge (CDM-ESD) protection strategies in a 28 nm thin-oxide CMOS process. The approach evaluates multiple protection topologies such as duo/trio diodes, and grounded-gate nMOS (ggNMOS), using very-fast Transmission Line Pulse (vf-TLP) testing. Failure analysis (FA) via Scanning Electron Microscopy (SEM) is used to correlate electrical degradation with physical damage post-stress. In-depth analysis is performed from three key perspectives: the influence of averaging window selection on I–V curve fidelity, extraction and interpretation of decoupling capacitance and energy dissipation efficiency under CDM-like stress. Results highlight both the strengths and limitations of each protection method under fast transients, offering insight into optimal ESD design for long interconnect paths. Practical enhancements to the vf-TLP setup are also discussed. This study identifies layout-induced failure mechanisms too. The proposed framework enhances CDM robustness validation and informs future ESD strategies in scaled nodes.