Low Overhead Self-Correction in Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flops for Space Applications

This paper presents a circuit solution for a Radiation-Hardening-by-Design (RHBD) Triple Modular Redundancy (TMR) flip-flop (FF) with self-correction (SC). The baseline TMR is enhanced with additional structures to filter transients and consists of modified latch stages that enable self-correction. Moreover, special spacings are introduced at layout-level to maintain the radiation hardness. The internal states of the triplicated flip-flops are compared and potential bit-flips are detected, internally corrected even though the clock activity has stopped. Thus, the proposed cell supports clock gating (CG) and stores the data reliably as discussed and confirmed by transistor-level simulation results. The novel self-correcting RHBD TMR flip-flop is arranged as a compatible standard cell and is optimized for a low overhead in power, area, and delay which is close to the performance of the standard unhardened counterpart. A prototype chip with special self-correcting test registers is fabricated in a 130 nm BiCMOS technology. As radiation experiments have shown, the proposed RHBD TMR flip-flop is robust up to an LET above 52.5 MeV cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> mg<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup>.