Optimizing Data Coupling and Control Coupling in Multi-Core Avionic Software: A Case Study with Xilinx Ultrascale+ Processors

This paper investigates the impact of multi-core interference on safety-critical avionic software running on AMD Xilinx Zynq Ultrascale+ MPSoC processors under the LynxOS RTOS. The case study analyzes data coupling and control coupling (DCCC), focusing on execution predictability, system reliability, and Worst-Case Execution Time (WCET). Additionally, static analysis is performed through data coupling and control coupling to provide insights into data dependencies, while dynamic analysis measures WCET under various combinations of data sizes and levels of interference injection. The paper offers guidance to comply with objectives in the safety standards (AC 20-193 [1], DO-178C [2]) while offering experimental mitigations for cache interference. Also, this paper examines the impact of large data buffering on system interference and provides actionable insights for developing reliable and certifiable multi-core avionics systems.