Full-Integer Spiking Neural Network Inference with RISC-V ISA Extensions for Radar-Based Gesture Recognition

Spiking neural networks (SNNs) offer energyefficient alternatives to conventional artificial neural networks (ANNs), making them suitable for real-time inference on resource-constrained edge devices. However, the reliance on floating-point operations (FLOPs) in spiking neuron states and dynamics often limits their applicability on hardware platforms without floating-point support and impacts the inference performance. In this work, we present hardware-aware optimizations to reduce the computational complexity, coupled with a full-integer spiking neural network (SNN) inference solution that eliminates FLOPs for radar-based hand gesture recognition (HGR). Furthermore, with an aim to develop a reduced instruction set computer 5th generation (RISC-V) based SNN accelerator, we present custom extensions to the RISC-V instruction set architecture (ISA). The proposed solution achieves an <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\approx 32$</tex> times overall speedup compared to the floating-point counterpart, in which <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\approx 11.5$</tex> times is achieved from the hardware-aware optimizations with full-integer solution, and an extra <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\approx 2.8$</tex> times from the custom RISC-V ISA extensions. The results highlight the feasibility of a full-integer SNN inference solution for a nontrivial HGR problem, and the potential of the RISC-V based SNN accelerator to enable efficient SNN inference.