EMI Mitigation and Inductance Reduction in SiC Power Modules Through Layout Optimization

Silicon Carbide (SiC) power modules operating at high frequencies face challenges from parasitic inductance and capacitance, leading to voltage overshoot and EMI. This study employs ANSYS Q3D and LTspice simulations to optimize a 1700 V/ 100 A SiC half-bridge module layout. The optimized design achieved a 41.5% reduction in power loop inductance (7.33 nH to 4.28 nH), 22.1% reduction in output capacitance, and 13.2% lower voltage overshoot. Commonmode current, a key EMI source, decreased by up to 29.5%. These gains, achieved through passive layout modifications, validate simulation-driven optimization for maximizing SiC module performance.