Analog Voltage-Shifter for 8-Bit Flash-SAR Hybrid Feed-Forward Architecture-Based ADC

Power efficiency presents a real bottleneck for highspeed Analog-to-Digital Converters (ADC) designers. In this proposed work, we employ a voltage shifter with a charge-injection (ci) cell-based ADC to perform analog-to-digital conversion alongside a flash ADC with coarse and fine binary searches. The ADC benefits from the small area and low power consumption of the ci-cell Digital-to-Analog Converter (DAC) to accommodate the additional power consumption of the comparators. The 2-bit additional Flash ADC finds the first Most Significant Bits (MSBs). After that, the ci-SAR ADC performs a binary search to find the rest of the bits. In between, the voltage shifts the sample to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\left[\frac{3}{4} V_{\text{DD}}, V_{\text{DD}}\right]$</tex> to reduce the SAR ADC's power consumption and improve its linearity. A system-level model is presented for the ADC, alongside a transistor-level simulation for the voltageshifter circuit, which consumes around <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$35 \mu\mathrm{W}$</tex>, with a maximum error of 3 Least Significant Bits (LSB) due to temperature variations from −20° C to 100° C.