On the Feasibility of Implementing a Four-Quadrant CMOS Analog Multiplier Using Only Digital Inverter Standard-Cells as Building Blocks

This work introduces the first four-quadrant CMOS analog multiplier circuit built entirely from digital inverter standard cells, without requiring any analog transistor-sizing methodologies. The multiplication operation is performed using a quadratic cancellation scheme in conjunction with a modified high-speed Nauta transconductor, which serves as summing point circuit. Consequently, the proposed multiplier achieves bandwidths of 2.2 GHz with x1 inverter cells and 3.8 GHz with x12 inverter cells, respectively. Additionally, the output offset issue is addressed by the same summing-point circuit. The power and silicon area consumption of both multipliers are 0.423 mW/(<inline-formula> <tex-math notation="LaTeX">$7.6~\mu $ </tex-math></inline-formula>m <inline-formula> <tex-math notation="LaTeX">$\times 14.73~\mu $ </tex-math></inline-formula>m) and 5.075 mW/(<inline-formula> <tex-math notation="LaTeX">$17.8~\mu $ </tex-math></inline-formula>m <inline-formula> <tex-math notation="LaTeX">$\times 14.73~\mu $ </tex-math></inline-formula>m), respectively. Mathematical modeling and post-layout transistor-level simulations using a TSMC 65 nm CMOS process, with a BSIM4 level 54 model, successfully validate the proposed multiplier. Finally, because the multiplication architecture is entirely composed of CMOS inverters (NOT gates), this circuit can be implemented and scaled for any advanced technology node that includes a digital standard-cell library.