A 2-GS/s 8-bit time-interleaved SAR ADC with offset calibration based on self-calibrating dynamic comparator in 40-nm CMOS

This paper presents an 8-bit, 2-GS/s, time-interleaved analog-to-digital converter (TI-ADC) for communication systems. Featuring self-calibrating dynamic comparators in the sub-SAR ADCs to minimize offset and improve overall linearity. It breaks through the limitation that the offset calibration of traditional comparators tends to introduce quiescent power consumption. A circuit and layout for the TI-ADC have been designed in 40nm CMOS. Operating at a 1-V supply voltage and 2-GHz clock frequency with a Nyquist frequency input, the design achieves a SNDR improvement from 42.11dB to 47.11dB, and a SFDR improvement from 60.46dB to 63.64dB. The power consumption is 25.79mW.