Design Principles for Accelerated Programmable Edge Computing in Future 6G Architectures

The growing demand for high throughput and ultra-low latency in emerging 6G networks requires moving service processing closer to end users and enabling powerful computational offloading within the network infrastructure. This work proposes Accelerated Programmable Edge Computing (APEC), a unified, flexible framework that combines high-performance CPU processing with hardware offloading capabilities provided by programmable network interface cards (NICs). APEC aims to enhance network performance with an adaptable platform merging high-level programming expressiveness with specialized hardware acceleration. Its architecture exposes custom primitives optimized for hardware and kernel-level offloading or user-space acceleration, via a Programmable Abstraction Interface, facilitating efficient execution of network functions. The framework provides high performance via multiple acceleration strategies. It optimizes data handling through high-speed software while advanced kernel-level processing further reduces latency, whereas performance-critical tasks are executed on specialized network hardware. This position paper provides the core components of the APEC framework, discussing their rationale and integration.