Wafer-Scale Low-Power 2D CFET Logic Enabled by Single-Crystal Dielectrics: Experimental Demonstration and 1-nm-Node Projection

We demonstrate a CFET technology that combines wafer-scale single-crystal TiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> dielectrics with vertically stacked n-MoS<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>/p-WSe<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> channels. A release–transfer process yields atomically flat TiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> films with sub-nanometre CET. The resulting CFET inverters switch rail-to-rail across a broad voltage range (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</inf> = 0.1 V to 1 V) with record-low standby power, high gain, and robust noise margins, validated by wafer-scale NAND/NOR gates. TCAD extrapolation at the 1nm node indicates that 4N2P six-transistor SRAM arrays on this platform surpass projections based on Si-GAA in terms of speed and energy, underscoring the viability of 2D semiconductors for next-generation logic.