Progress and Perspectives on p-GaN Cap Layer Etching Engineering Over p-GaN/AlGaN/GaN Heterojunctions

Gallium nitride (GaN)-based transistors with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i>-type GaN (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i>-GaN) gates are widely recognized as promising devices for power converter applications, due to their positive and stable threshold voltage, low on-resistance, and high breakdown field. However, the fabrication of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i>-GaN gate high electron mobility transistors (HEMTs) faces several key process challenges, among which the etching of the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i>-GaN layer has recently become particularly important. Given the emergence of novel <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i>-GaN etching techniques, a comprehensive review that encompasses scientific classification and systematic evaluation of these methods is essential. This paper aims to fill this gap by reviewing the latest fabrication technologies for forming <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i>-GaN gates in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i>-GaN/aluminum gallium nitride (AlGaN)/GaN heterojunctions. <p xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Firstly, the etching methods are categorized into self-terminating etching, dual-step cyclic etching, and plasma treatment techniques. These three classes are comprehensively summarized and compared in terms of etching rate, mechanisms, selectivity, and applicability. Self-terminated etching methods are divided into oxygen-based and fluorine-based systems, with a focus on the influence of critical process parameters on etch rate and selectivity. Subsequently, repetitive self-limiting etching techniques, including digital etching (DE) and atomic layer etching (ALE), are reviewed, with an emphasis on oxide-chloride and chloride-inert gas systems. Finally, plasma passivation processes are introduced as an alternative approach for achieving enhancement-mode <i>p</i>-GaN gate HEMTs. <p xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">This paper provides a summary and discussion of the key fabrication process of <i>p</i>-GaN gate devices—namely, the <i>p</i>-GaN cap layer etching engineering. It offers guidance for selecting appropriate etching methods under different application scenarios and provides valuable insights for the future development of GaN HEMTs.