Joint structure optimization to improve cell current in 3D NAND flash structures with misaligned dual decks

Abstract Misalignment in dual-deck 3D NAND flash induces additional electron trapping in the charge trap layer within the deck-to-deck joint region, thereby degrading the cell current ( I cell ). Technology computer-aided design simulation confirms that this I cell degradation worsens as the stacking level increases, which is attributed to the cumulative effect of parasitic joint resistance ( R Joint ). To address this issue, a comprehensively optimized cell structure is proposed, integrating material, structural, and operational solutions. In addition, this paper analyzed a trade-off mechanism, governed by “Word Line Control” and “Space Control” regimes, that dictates I cell performance depending on the electron trapped charge state. Furthermore, we demonstrate that the proposed final structure—integrating a multi-dielectric spacer (Si 3 N 4 /air/Si 3 N 4 , NAN), a locally optimized blocking oxide ( B OX ) width, and a convex channel structure—improves cell current and enhances operational stability. As a result, the proposed structure achieves a 39% improvement in I cell and a significantly wider program V PASS margin. This enhanced stability is physically attributed to the suppression of channel potential variations provided by the convex structure, which ensures a robust programming environment against neighbor-gate interference.