A 2.4-GHz Type-I Reference-Sampling Injection-Locked PLL With an RSPD-Based Injection Timing Calibration Loop

A type-I reference-sampling injection-locked phase-locked loop (RS-ILPLL) for low-jitter clock generation is presented. For the first time, the proposed architecture integrates a reference-sampling PLL (RSPLL) with an injection-locked PLL (IL-PLL), combining the wide lock range and inherent stability of the RSPLL with the noise-suppression capability of injection locking. An RSPD-based injection timing calibration loop is also introduced to precisely align the phase between the PLL and injection paths by compensating intrinsic delay mismatches. Fabricated in a 65-nm CMOS process, the prototype occupies a core area of 0.24 mm² and consumes 5.78 mW at 2.4-GHz. The RS-ILPLL achieves a 9.1 dB phase-noise improvement and an integrated RMS jitter of 92.6 fs (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FoM</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> = –253 dB, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FoM</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> = –266.8 dB), corresponding to a 72 % reduction compared with a conventional type-I RSPLL. Owing to its stable loop dynamics and compact implementation, the proposed RS-ILPLL demonstrates fast locking, low power, and robust low noise performance without requiring an auxiliary FLL. These features make it highly suitable for next-generation high-speed clocking applications.