Demonstrating the Electro-Thermal Dynamics in Complementary FETs: Quantifying the Role of Self-Heating and Grain Effect Intercoupling

The vertical stacking of sheets and separating them by a dielectric raises severe thermal and geometrical reliability concerns in the complementary field effect transistor (CFET). Using well-calibrated TCAD models, we investigated the impact of the self-heating effect (SHE) and the role of dielectric separation wall (D<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SW</sub>) in electro-thermal coupling. The resulting thermal crosstalk due to D<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SW</sub> shows an increase in temperature of 2.09% (1.60%) at the pFET (nFET) when nFET (pFET) is in the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> state. Furthermore, the metal grain granularity (MGG) is a vital factor that affects the electro-thermal characteristics. It offers the randomized metal work function (WF), thereby significantly causing the shift in threshold voltage (V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub>). A semi-empirical model is proposed to define the ratio of effective grain size to gate (RGG) area, which provides insight into the grain boundaries and their optimization in CFET. In addition, the significance of the extension region (L<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EXT</sub>) in electro-thermal performance is explored, as L<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EXT</sub> offers series resistance, which modulates thermal resistance. The increase in L<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EXT</sub> from 3 to 7 nm results in decreased lattice temperature (T<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub>) by ~29 K; however, it increases the series resistance and causes the decrease in <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> current (I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub>) by 28% (25%) in nFET (pFET). At last, we predicted the device’s lifetime based on V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift (i.e., change in V<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\text {th}}= \pm 50$</tex-math> </inline-formula> mV). Thus, the proposed analysis is worth exploring for the reliability-aware CFET design in sub-3 nm nodes.