Adaptive Patterning®: Unlocking Scalable Density in Embedded Bridge Die Interposer

The rapid advancement of artificial intelligence (AI) has created an escalating demand for high-density interposers to support increasingly complex and powerful system architectures. While silicon interposers are currently the predominant solution—particularly for processor-to-memory integration—molded fan-out embedded bridge die interposers are emerging as a highly scalable and cost-effective alternative for large AI devices. However, conventional manufacturing methods for embedded bridge die interposers face critical challenges, such as: extremely tight die placement tolerances <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\leq 1 \mu m)$</tex>, oversized via capture pads, which limit routing density, restricted bridge die aspect ratios reducing design flexibility. These limitations contribute to higher production costs, limited scalability, and yield issues—especially at volume. This paper introduces an innovative design using Adaptive Patterning ® (AP), a design-adaptive approach that fundamentally redefines the lithographic process. Leveraging maskless laser direct imaging (LDI), AP generates a unique, optimized pattern for each individual device, dynamically aligning interconnect features, such as dielectric vias and copper redistribution layers (RDLs), to the exact die placement on the molded reconstituted wafer or panel. This fully compensates for die shift introduced during assembly, ensuring accurate alignment and robust performance.