Design and Implementation of a 32-bit RISC-V Pipelined Processor by using Verilog for IoT

In this paper, we discuss the need for customized, resource-efficient processing units in low-power Internet of Things (IoT) edge devices. The challenge in these environments is to balance high instruction throughput with a small hardware footprint and low energy use. We present the design and implementation of a 32-bit RISC-V pipelined processor using Verilog HDL. This processor is used in a real-time system that integrates humidity sensing and data display, and it runs on an FPGA platform. Sensor data comes in via UART, gets processed by the RISC-V core, and is sent to an ESP32 microcontroller for output display. The proposed design has a traditional five-stage pipeline (IF, ID, EX, MEM, WB) made for embedded applications with memory-mapped peripheral interfaces. Simulation and synthesis results on an Artix-7 FPGA show that the design is functionally correct, uses hardware efficiently (approximately 18percent LUT utilization), and is suitable for real-time, low-power IoT systems.