Design and Implementation of A DSP-Enhanced RISC-V Pipelined Processor Using Verilog HDL

This paper presents the design and implementation of a 5-stage pipelined RISC-V processor architecture augmented with DSP (Digital Signal Processing) capabilities using Verilog HDL. The processor architecture integrates essential pipeline stages-Instruction Fetch, Decode, Execute, Memory Access, and Write Back-enhanced by advanced modules such as hazard detection and forwarding units to support efficient instructionlevel parallelism. A specialised ALU is developed to support both arithmetic/logical operations, as well as DSP-centric computations, optimising performance for signal processing applications. The system is verified using a custom testbench in Vivado 2025.1, and waveform analysis confirms accurate pipeline behaviour and DSP instruction execution. This processor is targeted for embedded and real-time systems requiring lowpower, high-performance computation with programmable logic integration.