A 2Tb 4b/Cell 6-Plane 3D-Flash Memory with 37.6Gb/mm ² Bit Density and >85MB/s Write Throughput

A 332-WL-layer stacked 2Tb 4b/Cell 6-plane 3D Flash memory achieves an areal density of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$37.6 \text{Gb} / \text{mm}^{2}$</tex>. An 8 kB -physical and 16 kB -logical page architecture realizes a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&lt;65 \mu \mathrm{s}$</tex> read latency and a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&gt;85 \text{MB} / \mathrm{s}$</tex> program throughput. Write throughput is enhanced by 4.2% through voltage-level sensing based on SEN2-LBUS coupling, and an additional 8% by reduced verify operations using 4 check points. A fast SLC burst programming technique reduces program time by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\sim 11 {\%}$</tex>.