A 12b 12GS/s Two-Way Interleaved Pipeline ADC with Integrated Broadband RF VGA in 5nm

A 12b <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$12 \text{GS} / \mathrm{s}$</tex> ADC with an integrated broadband RF VGA is implemented in a 5 nm FinFET process. This combination achieves a programmable input range of 36 dB from <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$250 \text{mV}_{\text{ppd }}$</tex> to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$16 \mathrm{V}_{\text{ppd }}$</tex>, bandwidth of 8.5 GHz, SNDR of 49 dB, SFDR of 70 dBc (with a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5.1 \text{GHz},-1 \text{dBFS}$</tex> input tone), and a single interleaving spur (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&lt;-90 \text{dBc}$</tex>) between DC and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{F}_{\mathrm{s}} / 2$</tex>. Two pipeline-stage architectures, “Flash Early-Trigger” and “Embedded SHA”, enable 6GS/s in a 12b sub-ADC, which is key to achieve two-way interleaving at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$12 \text{GS} / \mathrm{s}$</tex>.