8.2 A 32Gb/s 12.35Tb/s/mm ² 0.36pJ/b UCIe-Like Die-to-Die Interface Featuring Edge-Triggered Transceivers in 3nm with Active LSI Packaging

This paper presents edge-triggered transceivers (ETT), enabling a 32Gb UCle-like chiplet interconnect when integrated within an active local silicon interconnect (aLSI). The ETT achieves power consumption of 0.07pJ/b and supports compact top-die TX/RX designs while optimizing 0.36pJ/b energy efficiency and 12.35Tb/s/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area bandwidth density. It demonstrates a 32Gb/s die-to-die link at 0.75V with 20.46ps eye width (65% UI) and 530mV eye height across 64 lanes in a 3nm CMOS process.