A 3nm, 400TOPS, 1080k DMIPS SoC with Chiplet Support for ASIL D Automotive Cross-Domain Applications

This paper presents a 3 nm SoC, designed for software defined vehicles, integrating various functions for zone-based computing. The chip includes a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1,080 \text{kDMIPS}$</tex> APU, 400TOPS NPU and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$51.2 \text{GB} / \mathrm{s}$</tex> inter-chip bandwidth. Functional safety is ensured by RegionID-based FFI over UCle. Power efficiency is achieved with fine-gating across <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$90+$</tex> power domains with enhanced IR-drop control and ASIL D-compliant DCLS. Hierarchical mCPGs reduce clock latency. The chip supports low-power modes such as Sentry and CPD.