Threshold‐Voltage Modulation and N ₂ O Plasma Passivation for Enhanced Retention and Memory Window in Capacitorless 2T0C DRAM Oxide Thin‐Film Transistors

Capacitorless two-transistor-zero-capacitor (2T0C) dynamic random-access memories (DRAMs) offer scalability, simplified processing, and design flexibility by eliminating storage capacitors. We propose 2T0C DRAMs using aluminum-doped indium tin zinc oxide (Al:ITZO) thin-film transistors (TFTs) that enhance both retention time and memory window through device-level engineering. To suppress off-state leakage, N₂O plasma treatment was applied, which enabled fine-tuning the threshold voltage (V_th) control via oxygen vacancy reduction, as confirmed by XPS analysis. Additionally, by adjusting the channel width-to-length (W/L) ratio of the read transistor (RTR), three key objectives were achieved. First, the write transistor (WTR) Vth was also engineered to enable hold-state operation at 0 V write word line (WWL), enabling ultra-low-power operation. Second, optimization of the RTR W/L ratio effectively suppressed charge loss, resulting in significantly improved retention characteristics. Third, the memory window was maximized by balancing the intrinsic trade-off between the RTR Vth and on-current (_I _on). As a result, we achieved retention times exceeding 1000 s and a ∼13-fold increase in memory window. These results demonstrate the feasibility of Al:ITZO-based 2T0C DRAMs for next-generation memory systems with improved scalability and energy efficiency.